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om .c 4U et 2Mb SYNCBURSTTM he SRAM S ta a D . FEATURES w w w
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM MT58L128L18D, MT58L64L32D, MT58L64L36D
3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle Deselect
* Fast clock and OE# access times * Single +3.3V +0.3V/-0.165V power supply (VDD) * Separate +3.3V isolated output buffer supply (VDDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os and control signals * Internally self-timed WRITE cycle * Burst control pin (interleaved or linear burst) * Automatic power-down * 100-pin TQFP package * Low capacitive bus loading * x18, x32, and x36 options available
OPTIONS
* Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz * Configurations 128K x 18 64K x 32 64K x 36 * Packages 100-pin TQFP
* Operating Temperature Range Commercial (0C to +70C)
MT58L128L18DT-10
m o .c U t4 e e h S ta a .D w w w
*JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP*
MARKING
-6 -7.5 -10
MT58L128L18D MT58L64L32D MT58L64L36D T
None
Part Number Example:
GENERAL DESCRIPTION
The Micron(R) SyncBurstTM SRAM family employs high- speed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron's 2Mb SyncBurst SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls
(c)2002, Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
om .c 4U et he aS at .D w w w
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM 128K x 18
17 SA0, SA1, SA MODE ADV# CLK ADDRESS REGISTER 17 15 17
2
SA0-SA1 SA1'
BINARY Q1 COUNTER AND LOGIC CLR Q0
SA0'
ADSC# ADSP# BYTE "b" WRITE REGISTER
9 BYTE "b" WRITE DRIVER
9 128K x 9 x 2 MEMORY ARRAY 9 18 SENSE 18 AMPS
BWb#
OUTPUT 18 REGISTERS
OUTPUT BUFFERS
18
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE "a" WRITE REGISTER
9
BYTE "a" WRITE DRIVER
E
DQs DQPa DQPb
ENABLE REGISTER
18
PIPELINED ENABLE 2
INPUT REGISTERS
FUNCTIONAL BLOCK DIAGRAM 64K x 32/36
16 SA0, SA1, SA
ADDRESS REGISTER
16
14 SA0-SA1
16
MODE ADV# CLK SA1' Q1 BINARY COUNTER SA0' CLR Q0
ADSC# ADSP# BWd# BYTE "d" WRITE REGISTER BYTE "c" WRITE REGISTER
9
BYTE "d" WRITE DRIVER BYTE "c" WRITE DRIVER BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER
9
BWc#
9
9
64K x 8 x 4 (x32) 64K x 9 x 4 (x36) 36 SENSE AMPS 36
OUTPUT REGISTERS 36
BWb#
BYTE "b" WRITE REGISTER
9
9
MEMORY ARRAY
OUTPUT BUFFERS E
36
DQs DQPa DQPb DQPb DQPb
BWa# BWE# GW# CE# CE2 CE2# OE#
BYTE "a" WRITE REGISTER
9
9
ENABLE REGISTER
36
PIPELINED ENABLE 4
INPUT REGISTERS
NOTE: Functional Block Diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
DQc pins and DQPc; BWd# controls DQd pins and DQPd. GW# LOW causes all bytes to be written. Parity pins are only available on the x18 and x36 versions. The device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. Micron's 2Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for Pentium(R) and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet.
TQFP PIN ASSIGNMENT TABLE
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x32/x36 NC/DQPc** DQc DQc VDDQ VSS NC DQc NC DQc DQb DQc DQb DQc VSS VDDQ DQb DQc DQb DQc VDD VDD NC VSS DQb DQd DQb DQd VDDQ VSS DQb DQd DQb DQd DQPb DQd NC DQd x18 NC NC NC PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NC/DQPd** MODE SA SA SA SA SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA SA NC/SA* PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x32/x36 NC/DQPa** DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb x18 NC NC NC PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 x32/x36 VSS VDDQ DQb DQb NC/DQPb** SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA
NC NC SA
NC NC
*Pin 50 is reserved for address expansion. **No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
PIN ASSIGNMENT (Top View) 100-Pin TQFP
SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
NC/SA* SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE
SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC NC/DQPb** NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb NC DQb DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb VDD VSS VDD NC NC VDD ZZ VSS DQa DQb DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ DQa NC DQa NC NC/DQPa** NC
x32/x36
NC/SA* SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE
*Pin 50 is reserved for address expansion. **No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
NC/DQPc** DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd**
4
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18 x32/x36 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 37 37 36 36 32-35, 44-49, 32-35, 44-49, 80-82, 99, 81, 82, 99, 100 100 93 94 - - 93 94 95 96
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated.
87
87
BWE#
Input
88
88
GW#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
64
64
ZZ
Input
97
97
CE2
Input
86 83
86 83
OE# ADV#
Input Input
(continued on next page)
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18 84 x32/x36 84 SYMBOL ADSP# TYPE Input DESCRIPTION Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating.
85
85
ADSC#
Input
31
31
MODE
Input
(a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69, 13, 18, 19, 72-75, 78, 79 22, 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 74 24 - - 51 80 1 30
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa pins; Byte "b" Output is DQb pins. For the x32 and x36 versions, Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK.
DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD VDDQ VSS NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these pins are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.
14, 15, 41, 65, 14, 15, 41, 65, 91 91 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 5, 10, 17, 21, 5, 10, 17, 21, 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 38, 39, 42, 43 38, 39, 42, 43 1-3, 6, 7, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 50 16, 66
Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND.
DNU NC
- -
Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation.
50
NC/SA
-
No Connect: This pin is reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
6
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X00 X...X11 X...X10 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X10 X...X11 X...X00 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X00 X...X01 X...X10
Partial Truth Table For WRITE COMMANDS (x18)
FUNCTION READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes GW# H H H H H L BWE# H L L L L X BWa# X H L H L X BWb# X H H L L X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW# H H H H L BWE# H L L L X BWa# X H L L X BWb# X H H L X BWc# X H H L X BWd# X H H L X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
TRUTH TABLE
ADDRESS USED Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current OPERATION CE# CE2# CE2 H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP# ADSC# ADV# WRITE# OE# X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
8
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to Vss .................................... -0.5V to +4.6V Voltage on VDDQ Supply Relative to Vss .................................... -0.5V to +4.6V VIN ............................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) ............ -55C to +150C Junction Temperature** .................................... +150C Short Circuit Output Current ........................... 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C TA +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA CONDITIONS SYMBOL VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.0 -0.3 -1.0 -1.0 2.4 - 3.135 3.135 MAX VDD + 0.3 0.8 1.0 1.0 - 0.4 3.6 VDD UNITS V V A A V V V V NOTES 1, 2 1, 2 3
1, 4 1, 4 1 1, 5
NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together for 3.3V I/O.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
9
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(0C TA +70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; All inputs VIL or VIH; Cycle time tKC MIN; VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN SYMBOL IDD TYP 100 -6 340 -7.5 280 -10 225 UNITS NOTES mA 1, 2, 3
IDD1
30
85
70
65
mA
1, 2, 3
CMOS Standby
ISB2
0.5
10
10
10
mA
2, 3
TTL Standby
ISB3
6
25
25
25
mA
2, 3
Clock Running
ISB4
30
85
70
65
mA
2, 3
TQFP CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25C; f = 1 MHz; VDD = 3.3V SYMBOL CI CO CA CCK TYP 2.7 4 2.5 2.5 MAX 3.5 5 3.5 3.5 UNITS pF pF pF pF NOTES 4 4 4 4
NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 4. This parameter is sampled.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
10
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL JA JC TYP 40 8 UNITS NOTES C/W C/W 1 1
NOTE: 1. This parameter is sampled.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0C TA +70C; VDD = +3.3V +0.3V/-0.165V)
-6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) SYMBOL
tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH
MIN 6.0
MAX
MIN 7.5
-7.5 MAX
-10 MIN 10 MAX UNITS ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
166 1.7 1.7 3.5 1.5 1.5 3.5 3.5 0 3.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0 1.5 1.5 1.9 1.9
133 3.2 3.2 4.0 1.5 1.5 4.0 4.0 0 4.0 2.2 2.2 2.2 2.2 2.2 2.2 0.5 0.5 0.5 0.5 0.5 0.5
100
2 2
5.0
5.0 5.0 4.5
3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 (VDDQ = +3.3V +0.3V/-0.165V) unless otherwise noted. 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2. 4. This parameter is sampled. 5. Transition is measured 500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. 7. OE# is a "Don't Care" when a byte write enable is sampled LOW. 8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V .................... VIL = (VDD/2.2) - 1.5V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... VDD/2.2 Output reference levels ............................ VDDQ/2.2 Output load ............................. See Figures 1 and 2
Output Load Equivalents
Q Z O= 50 50 V = 1.5V T
Figure 1
+3.3V
LOAD DERATING CURVES
The Micron 128K x 18, 64K x 32, and 64K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves.
Q 351
317 5pF
Figure 2
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current
NOTE: 1. This parameter is sampled.
CONDITIONS ZZ VIH
SYMBOL ISB2Z
tZZ tRZZ tZZI tRZZI
MIN
MAX 10 2(tKC)
UNITS mA ns ns ns ns
NOTES 1 1 1 1
2(tKC) 2(tKC) 0
SNOOZE MODE WAVEFORM
CLK
t ZZ t RZZ
ZZ
t ZZI
I
SUPPLY I ISB2Z t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
READ TIMING
tKC
CLK
tKH tADSS tADSH tKL
ADSP#
tADSS tADSH
ADSC#
tAS tAH
ADDRESS
A1
tWS tWH
A2
A3 Burst continued with new base address.
GW#, BWE#, BWa#-BWd#
tCES tCEH
Deselect (NOTE 4) cycle.
CE# (NOTE 2) ADV#
tAAS
tAAH
ADV# suspends burst. OE# (NOTE 3)
t KQLZ t OEHZ tOEQ t OELZ tKQ tKQX t KQHZ
Q
High-Z
Q(A1)
t KQ
Q(A2) (NOTE 1)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURST READ
Burst wraps around to its initial state.
DON'T CARE
UNDEFINED
READ TIMING PARAMETERS
-6 SYM
tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ
MIN 6.0
MAX 166
-7.5 MIN MAX 7.5 133 1.9 1.9
-10 MIN 10 100 3.2 3.2 MAX UNITS ns MHz ns ns ns ns ns 5.0 5.0 0 4.5 ns ns ns ns SYM tAS tADSS
tAAS tWS tCES tAH tADSH tAAH tWH tCEH
-6 MIN 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 MAX
-7.5 MIN 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 MAX MIN 2.2 2.2 2.2 2.2 2.2 0.5 0.5 0.5 0.5 0.5
-10 MAX UNITS ns ns ns ns ns ns ns ns ns ns
1.7 1.7 3.5 1.5 1.5 3.5 3.5 0 3.5
4.0 1.5 1.5 4.0 4.0 0 4.0 1.5 1.5
5.0
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
WRITE TIMING
t KC
CLK
tKH tADSS tADSH tKL
ADSP#
tADSS tADSH
ADSC# extends burst.
tADSS tADSH
ADSC#
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP# initiates burst.
A3
tWS tWH
BWE#, BWa#-BWd# (NOTE 5)
tWS tWH
GW#
tCES tCEH
CE# (NOTE 2) ADV# (NOTE 4) OE# (NOTE 3)
tDS tDH
tAAS tAAH
ADV# suspends burst.
D
High-Z
tOEHZ
D(A1)
D(A2)
D(A2 + 1) (NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED
WRITE TIMING PARAMETERS
-6 SYM
tKC fKF tKH tKL tOEHZ tAS tADSS tAAS tWS
MIN 6.0
MAX 166
-7.5 MIN MAX 7.5 133 1.9 1.9
-10 MIN 10 100 3.2 3.2 MAX UNITS ns MHz ns ns ns ns ns ns ns SYM tDS
tCES tAH tADSH tAAH tWH tDH tCEH
-6 MIN 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 MAX
-7.5 MIN MAX 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5
-10 MIN 2.2 2.2 0.5 0.5 0.5 0.5 0.5 0.5 MAX UNITS ns ns ns ns ns ns ns ns
1.7 1.7 3.5 1.5 1.5 1.5 1.5
4.0 1.5 1.5 1.5 1.5 2.2 2.2 2.2 2.2
4.5
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
READ/WRITE TIMING
tKC
CLK
tKH tADSS tADSH tKL
ADSP#
ADSC#
tAS tAH
ADDRESS BWE#, BWa#-BWd# (NOTE 4) CE# (NOTE 2) ADV#
A1
A2
A3
tWS tWH
A4
A5
A6
tCES
tCEH
OE#
tKQ tDS tDH tOELZ
D
High-Z
tKQLZ
tOEHZ
D(A3) (NOTE 1) Q(A4) Single WRITE Q(A4+1) BURST READ Q(A4+2) Q(A4+3)
D(A5)
D(A6)
Q
High-Z
Q(A1) Back-to-Back READs (NOTE 5)
Q(A2)
Back-to-Back WRITEs DON'T CARE UNDEFINED
READ/WRITE TIMING PARAMETERS
-6 SYM
tKC fKF tKH tKL tKQ tKQLZ tOELZ tOEHZ tAS
MIN 6.0
MAX 166
-7.5 MIN MAX 7.5 133 1.9 1.9
-10 MIN 10 100 3.2 3.2 MAX UNITS ns MHz ns ns ns ns ns ns ns SYM
tADSS tWS tDS tCES tAH tADSH tWH tDH tCEH
-6 MIN 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 MAX
-7.5 MIN MAX 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5
-10 MIN 2.2 2.2 2.2 2.2 0.5 0.5 0.5 0.5 0.5 MAX UNITS ns ns ns ns ns ns ns ns ns
1.7 1.7 3.5 1.5 0 3.5 1.5
4.0 1.5 0 4.0 1.5 2.2 1.5 0
5.0
4.5
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
+0.10 -0.20 20.10 0.10 22.10 0.65 TYP 0.32 +0.06 -0.10 0.625 SEE DETAIL A
14.00 0.10 16.00 0.20
PIN #1 ID 0.15
+0.03 -0.02
1.40 0.05 GAGE PLANE
1.60 MAX 0.10 0.10 +0.10 -0.05 0.25 DETAIL A 1.00 TYP 0.60 0.15
NOTE: 1. All dimensions in millimeters MAX or typical here noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
DATA SHEET DESIGNATIONS
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM
REVISION HISTORY
Added "NOT RECOMENDED FOR NEW DESIGNS," REV. C, Pub. 11/02, FINAL ........................ November/22/02 Removed 165-pin FBGA package, Rev. 6/01 .................................................................................................. June/7/01 Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/00 CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 7pF CO; TYP 4pF from 6pF; MAX. 5pF from 7pF CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF Removed IT References, REV 7/00, FINAL ..................................................................................................... July/14/00 Added FBGA Part Marking Guide Added Revision History to Datasheet Removed IT from Part Number Example, REV 6/00, FINAL ....................................................................... June/21/00 Added # of datalines to the databus in x32/36 Block Diagram Added Note - "Preliminary Package Data" to FBGA Capacitance and Thermal Resistance Tables Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 - Rev. C, Pub. 11/02
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.

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